FireSim generates SoC models by transforming RTL emitted by a Chisel generator, specifically the Rocket SoC generator. Subject to conditions outlined in Restrictions on Target-RTL, if it can be generated by Rocket Chip, it can be simulated in FireSim.

Restrictions on Target-RTL

Current limitations in MIDAS place the following restrictions on the (FIR)RTL that can be transformed and thus used in FireSim:

  1. The RTL must not contain multiple clock domains.
  2. The RTL must not contain multi-cycle paths.
  3. The RTL must not contain black boxes, with the exception of Rocket Chip’s async reset register.
  4. Asynchronous reset must only be implemented using Rocket Chip’s black box async reset. These are replaced with synchronously reset registers using a FIRRTL transformation.

Generating Different Target-RTL

FireSim provides Rocket Chip-derived RTL generators for four target-design classes (set with the make variable DESIGN, see sim/src/main/scala/Targets.scala). Like any other Rocket Chip-derived generator, a different parameterization is selected with a Chisel configuration (make variable TARGET_CONFIG, see sim/src/main/scala/TargetConfigs.scala). Since I/O and DRAM models are not generated by Rocket Chip but by MIDAS, their parameterization is captured in a second Chisel configuration (make variable PLATFORM_CONFIG, see sim/src/main/scala/SimConfigs.scala).

We give examples of generating different targets using these three variables in the sections that follow.

Rocket-based SoCs

Two design classes use the Rocket scalar in-order pipelines.

Single core, Rocket pipeline (default)

make DESIGN=FireSim TARGET_CONFIG=FireSimRocketChipConfig

Single-core Rocket pipeline, without a network interface

make DESIGN=FireSimNoNIC TARGET_CONFIG=FireSimRocketChipConfig

Quad-core Rocket pipeline

make DESIGN=FireSim TARGET_CONFIG=FireSimRocketChipQuadCoreConfig

Other configurations are predefined in TODO.

BOOM-based SoCs (Beta)

Note: BOOM support is in beta as we resolve some issues with Linux boot. See issue #12.

Two design classes use the BOOM scalar in-order pipelines.

Single-core BOOM pipeline

make DESIGN=FireBoom TARGET_CONFIG=FireSimBoomConfig

Single-core BOOM pipeline, without a network interface

make DESIGN=FireBoomNoNIC TARGET_CONFIG=FireSimBoomConfig

Changing The DRAM Model

MIDAS can generate a space of different DRAM model instances we give some typical ones here. These targets use the Makefile-defined defaults of DESIGN=FireSim TARGET_CONFIG=FireSimRocketChipConfig.

Quad-rank DDR3 first-come first-served memory access scheduler


Quad-rank DDR3 first-ready, first-come first-served memory access scheduler


As above, but with an 4 MiB (max capacity) last-level-cache model