FireSim
1.6.0

Getting Started:

  • 1. FireSim Basics
    • 1.1. Two common use cases:
      • 1.1.1. Single-Node Simulation, in Parallel
      • 1.1.2. Datacenter/Cluster Simulation
    • 1.2. Other Use Cases
    • 1.3. Background/Terminology
    • 1.4. Using FireSim/The FireSim Workflow
  • 2. Initial Setup/Installation
    • 2.1. First-time AWS User Setup
      • 2.1.1. Creating an AWS Account
      • 2.1.2. AWS Credit at Berkeley
      • 2.1.3. Requesting Limit Increases
    • 2.2. Configuring Required Infrastructure in Your AWS Account
      • 2.2.1. Select a region
      • 2.2.2. Key Setup
      • 2.2.3. Check your EC2 Instance Limits
      • 2.2.4. Start a t2.nano instance to run the remaining configuration commands
      • 2.2.5. Run scripts from the t2.nano
      • 2.2.6. Terminate the t2.nano
      • 2.2.7. Subscribe to the AWS FPGA Developer AMI
    • 2.3. Setting up your Manager Instance
      • 2.3.1. Launching a “Manager Instance”
        • 2.3.1.1. Access your instance
        • 2.3.1.2. Key Setup, Part 2
      • 2.3.2. Setting up the FireSim Repo
      • 2.3.3. Completing Setup Using the Manager
  • 3. Running FireSim Simulations
    • 3.1. Running a Single Node Simulation
      • 3.1.1. Building target software
      • 3.1.2. Setting up the manager configuration
      • 3.1.3. Launching a Simulation!
        • 3.1.3.1. Starting the Run Farm
        • 3.1.3.2. Setting up the simulation infrastructure
        • 3.1.3.3. Running a simulation!
    • 3.2. Running a Cluster Simulation
      • 3.2.1. Returning to a clean configuration
      • 3.2.2. Building target software
      • 3.2.3. Setting up the manager configuration
      • 3.2.4. Launching a Simulation!
        • 3.2.4.1. Starting the Run Farm
        • 3.2.4.2. Setting up the simulation infrastructure
        • 3.2.4.3. Running a simulation!
  • 4. Building Your Own Hardware Designs (FireSim FPGA Images)
    • 4.1. Amazon S3 Setup
    • 4.2. Build Recipes
    • 4.3. Running a Build

Advanced Docs:

  • Manager Usage (the firesim command)
    • 1. Overview
      • 1.1. “Inputs” to the Manager
      • 1.2. Logging
    • 2. Manager Command Line Arguments
      • 2.1. --runtimeconfigfile FILENAME
      • 2.2. --buildconfigfile FILENAME
      • 2.3. --buildrecipesconfigfile FILENAME
      • 2.4. --hwdbconfigfile FILENAME
      • 2.5. --overrideconfigdata SECTION PARAMETER VALUE
      • 2.6. TASK
    • 3. Manager Tasks
      • 3.1. firesim managerinit
      • 3.2. firesim buildafi
      • 3.3. firesim shareagfi
      • 3.4. firesim launchrunfarm
      • 3.5. firesim terminaterunfarm
      • 3.6. firesim infrasetup
      • 3.7. firesim boot
      • 3.8. firesim kill
      • 3.9. firesim runworkload
      • 3.10. firesim runcheck
    • 4. Manager Configuration Files
      • 4.1. config_runtime.ini
        • 4.1.1. [runfarm]
        • 4.1.2. [targetconfig]
        • 4.1.3. [workload]
      • 4.2. config_build.ini
        • 4.2.1. [afibuild]
        • 4.2.2. [builds]
        • 4.2.3. [agfistoshare]
        • 4.2.4. [sharewithaccounts]
      • 4.3. config_build_recipes.ini
        • 4.3.1. Build definition sections, e.g. [awesome-firesim-config]
      • 4.4. config_hwdb.ini
        • 4.4.1. [NAME_GOES_HERE]
        • 4.4.2. Add more hardware config sections, like [NAME_GOES_HERE_2]
    • 5. Manager Environment Variables
      • 5.1. FIRESIM_RUNFARM_PREFIX
    • 6. Manager Network Topology Definitions (user_topology.py)
      • 6.1. user_topology.py contents:
    • 7. AGFI Metadata/Tagging
  • Workloads
    • Defining Custom Workloads
      • Uniform Workload JSON
      • Non-uniform Workload JSON (explicit job per simulated node)
    • SPEC 2017
      • Intspeed
      • Intrate
    • Running Fedora on FireSim
    • ISCA 2018 Experiments
      • Prerequisites
      • Building Benchmark Binaries/Rootfses
      • Figure 5: Ping Latency vs. Configured Link Latency
      • Figure 6: Network Bandwidth Saturation
      • Figure 7: Memcached QoS / Thread Imbalance
      • Figure 8: Simulation Rate vs. Scale
      • Figure 9: Simulation Rate vs. Link Latency
      • Running all experiments at once
    • GAP Benchmark Suite
  • FireMarshal (alpha)
    • Quick Start
    • FireMarshal Commands
      • Core Options
        • --workdir
        • -i --initramfs
        • -v --verbose
      • build
        • -I -B
      • launch
        • -j --job
        • -s --spike
      • clean
      • test
        • -s --spike
        • -m testDir --manual testDir
      • install
    • Workload Specification
      • Example Configuration File
      • Bare-Metal Workloads
      • Configuration File Options
        • name
        • base
        • spike
        • linux-src
        • linux-config
        • host-init
        • post_run_hook
        • overlay
        • files
        • outputs
        • run
        • command
        • workdir
        • launch
        • jobs
        • bin
        • img
        • testing
  • Targets
    • Restrictions on Target RTL
    • Provided Target Designs
      • Target Generator Organization
      • Specifying A Target Instance
    • Rocket Chip Generator-based SoCs (firesim project)
      • Rocket-based SoCs
      • BOOM-based SoCs
      • Generating A Different FASED Memory-Timing Model Instance
    • Midas Examples (midasexamples project)
      • Examples
    • FASED Tests (fasedtests project)
      • Examples
  • Debugging
    • Debugging & Testing with RTL Simulation
      • Target-Level Simulation
      • MIDAS-Level Simulation
        • Examples
      • FPGA-Level Simulation
        • Usage
      • Scala Tests
    • Debugging Using FPGA Integrated Logic Analyzers (ILA)
      • Annotating Signals
      • Using the ILA at Runtime
    • Debugging Using TracerV
      • Building a Design with TracerV
      • Enabling Tracing at Runtime
      • Interpreting the Trace Result
    • Assertion Synthesis
      • Enabling Assertion Synthesis
      • Runtime Behavior
      • Related Publications
    • Printf Synthesis
      • Enabling Printf Synthesis
      • Runtime Arguments
      • Related Publications
  • Tutorial: Developing New Devices
    • Getting Started
    • Memory-mapped Registers
    • DMA and Interrupts
      • TileLink Client Port
      • TileLink Protocol and State Machine
      • Interrupts
    • Connecting Devices to Bus
      • SoC Mixin Traits
      • Top-Level Design and Configuration
    • Running Test Software
      • Debugging Verilog Simulation
    • Creating Simulation Model
  • Supernode - Multiple Simulated SoCs Per FPGA
    • Introduction
    • Building Supernode Designs
    • Running Supernode Simulations
    • Work in Progress!
  • Miscellaneous Tips
    • Add the fsimcluster column to your AWS management console
    • FPGA Dev AMI Remote Desktop Setup
    • Experimental Support for SSHing into simulated nodes and accessing the internet from within simulations
    • Navigating the FireSim Codebase
  • FireSim Asked Questions
    • I just bumped the FireSim repository to a newer commit and simulations aren’t running. What is going on?
    • Is there a good way to keep track of what AGFI corresponds to what FireSim commit?
FireSim
  • Docs »
  • Debugging
  • Edit on GitHub

Debugging¶

This section describes methods of debugging the target design and the simulation in FireSim.

Debugging:

  • Debugging & Testing with RTL Simulation
    • Target-Level Simulation
    • MIDAS-Level Simulation
    • FPGA-Level Simulation
    • Scala Tests
  • Debugging Using FPGA Integrated Logic Analyzers (ILA)
    • Annotating Signals
    • Using the ILA at Runtime
  • Debugging Using TracerV
    • Building a Design with TracerV
    • Enabling Tracing at Runtime
    • Interpreting the Trace Result
  • Assertion Synthesis
    • Enabling Assertion Synthesis
    • Runtime Behavior
    • Related Publications
  • Printf Synthesis
    • Enabling Printf Synthesis
    • Runtime Arguments
    • Related Publications
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© Copyright 2018, Sagar Karandikar, Howard Mao, Donggyu Kim, David Biancolin, Alon Amid, and Berkeley Architecture Research. Revision 688ecda9.

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