Debugging Using TracerV¶
FireSim can provide a cycle-by-cycle trace of the CPU’s architectural state over the course of execution. This can be useful for profiling or debugging. The tracing functionality is provided by the TracerV widget.
Building a Design with TracerV¶
In all FireChip designs TracerV is generated by default. Other targets can enable it by attaching a TracerV Bridge to the RISC-V trace port of one-or-more cores.
Enabling Tracing at Runtime¶
To improve simulation preformance, FireSim does not collect data from the
TracerV Bridge by default. To enable collection, modify the tracing section to your
Now when you run a workload, a trace output file will be placed in the
sim_slot_<slot #> directory on the F1 instance under the name TRACEFILE.
Tracing the entirety of a long-running job like a Linux-based workload can
generate a pretty large image, and you may only care about the state within a
certain timeframe. Therefore, FireSim allows you to specify a start cycle and
end cycle for collecting data. By default, it starts at cycle 0 and ends at
the last cycle of the simulation. To change this, modify the following under
the “tracing” section of your