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Getting Started:

  • 1. FireSim Basics
    • 1.1. Two common use cases:
      • 1.1.1. Single-Node Simulation, in Parallel
      • 1.1.2. Datacenter/Cluster Simulation
    • 1.2. Other Use Cases
    • 1.3. Background/Terminology
    • 1.4. Using FireSim/The FireSim Workflow
  • 2. Initial Setup/Installation
    • 2.1. First-time AWS User Setup
      • 2.1.1. Creating an AWS Account
      • 2.1.2. AWS Credit at Berkeley
      • 2.1.3. Requesting Limit Increases
    • 2.2. Configuring Required Infrastructure in Your AWS Account
      • 2.2.1. Select a region
      • 2.2.2. Key Setup
      • 2.2.3. Check your EC2 Instance Limits
      • 2.2.4. Start a t2.nano instance to run the remaining configuration commands
      • 2.2.5. Run scripts from the t2.nano
      • 2.2.6. Terminate the t2.nano
      • 2.2.7. Subscribe to the AWS FPGA Developer AMI
    • 2.3. Setting up your Manager Instance
      • 2.3.1. Launching a “Manager Instance”
        • 2.3.1.1. Access your instance
        • 2.3.1.2. Key Setup, Part 2
      • 2.3.2. Setting up the FireSim Repo
      • 2.3.3. Completing Setup Using the Manager
  • 3. Running FireSim Simulations
    • 3.1. Running a Single Node Simulation
      • 3.1.1. Building target software
      • 3.1.2. Setting up the manager configuration
      • 3.1.3. Launching a Simulation!
        • 3.1.3.1. Starting the Run Farm
        • 3.1.3.2. Setting up the simulation infrastructure
        • 3.1.3.3. Running a simulation!
    • 3.2. Running a Cluster Simulation
      • 3.2.1. Returning to a clean configuration
      • 3.2.2. Building target software
      • 3.2.3. Setting up the manager configuration
      • 3.2.4. Launching a Simulation!
        • 3.2.4.1. Starting the Run Farm
        • 3.2.4.2. Setting up the simulation infrastructure
        • 3.2.4.3. Running a simulation!
  • 4. Building Your Own Hardware Designs (FireSim FPGA Images)
    • 4.1. Amazon S3 Setup
    • 4.2. Build Recipes
    • 4.3. Running a Build

Advanced Docs:

  • Manager Usage (the firesim command)
    • 1. Overview
      • 1.1. “Inputs” to the Manager
      • 1.2. Logging
    • 2. Manager Command Line Arguments
      • 2.1. --runtimeconfigfile FILENAME
      • 2.2. --buildconfigfile FILENAME
      • 2.3. --buildrecipesconfigfile FILENAME
      • 2.4. --hwdbconfigfile FILENAME
      • 2.5. --overrideconfigdata SECTION PARAMETER VALUE
      • 2.6. --launchtime TIMESTAMP
      • 2.7. TASK
    • 3. Manager Tasks
      • 3.1. firesim managerinit
      • 3.2. firesim buildafi
      • 3.3. firesim tar2afi
      • 3.4. firesim shareagfi
      • 3.5. firesim launchrunfarm
      • 3.6. firesim terminaterunfarm
      • 3.7. firesim infrasetup
      • 3.8. firesim boot
      • 3.9. firesim kill
      • 3.10. firesim runworkload
      • 3.11. firesim runcheck
    • 4. Manager Configuration Files
      • 4.1. config_runtime.ini
        • 4.1.1. [runfarm]
        • 4.1.2. [targetconfig]
        • 4.1.3. [tracing]
        • 4.1.4. [autocounter]
        • 4.1.5. [workload]
        • 4.1.6. [hostdebug]
      • 4.2. config_build.ini
        • 4.2.1. [afibuild]
        • 4.2.2. [builds]
        • 4.2.3. [agfistoshare]
        • 4.2.4. [sharewithaccounts]
      • 4.3. config_build_recipes.ini
        • 4.3.1. Build definition sections, e.g. [awesome-firesim-config]
      • 4.4. config_hwdb.ini
        • 4.4.1. [NAME_GOES_HERE]
        • 4.4.2. Add more hardware config sections, like [NAME_GOES_HERE_2]
    • 5. Manager Environment Variables
      • 5.1. FIRESIM_RUNFARM_PREFIX
    • 6. Manager Network Topology Definitions (user_topology.py)
      • 6.1. user_topology.py contents:
    • 7. AGFI Metadata/Tagging
  • Workloads
    • Defining Custom Workloads
      • Uniform Workload JSON
      • Non-uniform Workload JSON (explicit job per simulated node)
    • FireMarshal
    • SPEC 2017
    • Running Fedora on FireSim
    • ISCA 2018 Experiments
      • Prerequisites
      • Building Benchmark Binaries/Rootfses
      • Figure 5: Ping Latency vs. Configured Link Latency
      • Figure 6: Network Bandwidth Saturation
      • Figure 7: Memcached QoS / Thread Imbalance
      • Figure 8: Simulation Rate vs. Scale
      • Figure 9: Simulation Rate vs. Link Latency
      • Running all experiments at once
    • GAP Benchmark Suite
    • [DEPRECATED] Defining Custom Workloads
      • Uniform Workload JSON
      • Non-uniform Workload JSON (explicit job per simulated node)
  • Targets
    • Restrictions on Target RTL
      • Including Verilog IP
      • Multiple Clock Domains
        • The Base Clock
        • Limitations:
    • Provided Target Designs
      • Target Generator Organization
      • Specifying A Target Instance
    • Rocket Chip Generator-based SoCs (firesim project)
      • Rocket-based SoCs
      • BOOM-based SoCs
      • Generating A Different FASED Memory-Timing Model Instance
    • Midas Examples (midasexamples project)
      • Examples
    • FASED Tests (fasedtests project)
      • Examples
  • Debugging in Software
    • Debugging & Testing with Meta-Simulation
      • Running Meta-Simulation
        • Examples
      • Understanding A Meta-Simulation Waveform
        • Module Hierarchy
        • Clock Edges and Event Timing
        • Finding The Source Of Simulation Stalls
      • Scala Tests
  • Debugging and Profiling on the FPGA
    • Capturing RISC-V Instruction Traces with TracerV
      • Building a Design with TracerV
      • Enabling Tracing at Runtime
      • Selecting a Trace Output Format
      • Setting a TracerV Trigger
        • No trigger
        • Target cycle trigger
        • Program Counter (PC) value trigger
        • Instruction value trigger
      • Interpreting the Trace Result
        • Human readable output
        • Binary output
        • Flame Graph output
      • Caveats
    • Assertion Synthesis: Catching RTL Assertions on the FPGA
      • Enabling Assertion Synthesis
      • Runtime Behavior
      • Related Publications
    • Printf Synthesis: Capturing RTL printf Calls when Running on the FPGA
      • Enabling Printf Synthesis
      • Runtime Arguments
      • Related Publications
    • AutoILA: Simple Integrated Logic Analyzer (ILA) Insertion
      • Enabling AutoILA
      • Annotating Signals
      • Setting a ILA Depth
      • Using the ILA at Runtime
    • AutoCounter: Profiling with Out-of-Band Performance Counter Collection
      • Chisel Interface
      • Enabling AutoCounter in Golden Gate
      • Rocket Chip Cover Functions
      • AutoCounter Runtime Parameters
      • AutoCounter CSV Output Format
      • Using TracerV Trigger with AutoCounter
      • AutoCounter using Synthesizable Printfs
      • Reset & Timing Considerations
    • TracerV + Flame Graphs: Profiling Software with Out-of-Band Flame Graph Generation
      • What are Flame Graphs?
      • Prerequisites
      • Enabling Flame Graph generation in config_runtime.ini
      • Producing DWARF information to supply to the TracerV driver
      • Modifying your workload description
      • Running a simulation
      • Caveats
    • Dromajo Co-simulation with BOOM designs
      • Building a Design with Dromajo
      • Running a FireSim Simulation
      • Troubleshooting Dromajo Simulations with Meta-Simulations
    • Debugging a Hanging Simulator
      • Case 1: Target hang.
      • Case 2: Simulator hang due to FPGA-side token starvation.
      • Case 3: Simulator hang due to driver-side deadlock.
      • Simulator Heartbeat PlusArgs
  • Supernode - Multiple Simulated SoCs Per FPGA
    • Introduction
    • Building Supernode Designs
    • Running Supernode Simulations
    • Work in Progress!
  • Miscellaneous Tips
    • Add the fsimcluster column to your AWS management console
    • FPGA Dev AMI Remote Desktop Setup
    • Experimental Support for SSHing into simulated nodes and accessing the internet from within simulations
    • Navigating the FireSim Codebase
    • Using FireSim CI
  • FireSim Asked Questions
    • I just bumped the FireSim repository to a newer commit and simulations aren’t running. What is going on?
    • Is there a good way to keep track of what AGFI corresponds to what FireSim commit?
    • Help, My Simulation Hangs!
    • Should My Simulator Produce Different Results Across Runs?
    • Is there a way to compress workload results when copying back to the manager instance?

Compiler (Golden Gate) Docs:

  • Overview & Philosophy
    • Golden Gate vs FPGA Prototyping
    • Why Use Golden Gate & FireSim
    • Why Not Golden Gate
    • How is Host-Decoupling Implemented?
  • Target Abstraction & Host Decoupling
    • The Target as a Dataflow Graph
    • Model Implementations
    • Expressing the Target Graph
    • Latency-Insensitive Bounded Dataflow Networks
  • Target-to-Host Bridges
    • Terminology
    • Target Side
      • Type Parameters:
      • Abstract Members:
    • What Happens Next?
    • Host Side
    • Compile-Time (Parameterization) vs Runtime Configuration
    • Target-Side vs Host-Side Parameterization
  • Bridge Walkthrough
    • UART Bridge (Host-MMIO)
      • Target Side
      • Host-Side BridgeModule
      • Host-Side Driver
      • Registering the Driver
      • Build-System Modifications
  • Simulation Triggers
    • Quick-Start Guide
      • Level-Sensitive Trigger Source
      • Distributed, Edge-Sensitive Trigger Source
    • Chisel API
      • Trigger Sources
      • Trigger Sinks
    • Trigger Timing
    • Limitations & Pitfalls
  • Optimizing FPGA Resource Utilization
    • Multi-Ported Memory Optimization
    • Multi-Threading of Repeated Instances
  • Output Files
    • Core Files
    • FPGA Synthesis Files
    • Meta-simulation Files
FireSim
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© Copyright 2018, Sagar Karandikar, Howard Mao, Donggyu Kim, David Biancolin, Alon Amid, and Berkeley Architecture Research. Revision 27bfce91.

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