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Getting Started
FireSim Basics
Background/Terminology
Initial Setup
AWS EC2 F2
First-time AWS User Setup
Configuring Required Infrastructure in Your AWS Account
Setting up your Manager Instance
Local FPGA System Setup
Chipyard-based Starter Tutorials
AWS EC2 F2
Setting up the FireSim Repo
Running Simulations
Running a Single Node Simulation
Running FireSim Simulations
Running a Cluster Simulation [Coming soon on F2]
Building Your Own Hardware Designs (FireSim Amazon FPGA Images)
Xilinx Alveo U200
FPGA Setup
FireSim Repo Setup
Running a Single Node Simulation
Building Your Own Hardware Designs
Xilinx Alveo U250
FPGA Setup
FireSim Repo Setup
Running a Single Node Simulation
Building Your Own Hardware Designs
Xilinx Alveo U280
FPGA Setup
FireSim Repo Setup
Running a Single Node Simulation
Building Your Own Hardware Designs
Xilinx VCU118
FPGA Setup
FireSim Repo Setup
Running a Single Node Simulation
Building Your Own Hardware Designs
RHS Research Nitefury II
FPGA Setup
FireSim Repo Setup
Running a Single Node Simulation
Building Your Own Hardware Designs
Xilinx Vitis
Initial Setup/Installation
Running a Single Node Simulation
Building Your Own Hardware Designs
Advanced Docs
Manager
Overview
Manager Command Line Arguments
Manager Tasks
Manager URI Paths
Manager Configuration Files
Manager Environment Variables
Manager Network Topology Definitions (user_topology.py)
AGFI Metadata/Tagging
Workloads
FireMarshal
[DEPRECATED] Defining Custom Workloads
Targets
Debugging in Software
Debugging & Testing with Metasimulation
Debugging and Profiling on FPGA
Capturing RISC-V Instruction Traces with TracerV
Assertion Synthesis: Catching RTL Assertions on the FPGA
Printf Synthesis: Capturing RTL printf Calls when Running on the FPGA
AutoILA: Simple Integrated Logic Analyzer (ILA) Insertion
AutoCounter: Profiling with Out-of-Band Performance Counter Collection
TracerV + Flame Graphs: Profiling Software with Out-of-Band Flame Graph Generation
Spike Co-simulation with BOOM designs
Debugging a Hanging Simulator
PlusArg Synthesis: Runtime Modification of RTL
Non-Source Dependency Management
Supernode - Multiple Simulated SoCs Per FPGA
FireAxe: Partitioning onto Multiple FPGAs
FireAxe Overview
Running Fast Mode Simulations
Running Exact Mode Simulations
Running NoC Partition Mode Simulations
Miscellaneous Tips
Miscellaneous Tips
Adding support for a new FPGA
Using FireSim without Chipyard
FireSim Asked Questions
Compiler (Golden Gate) Docs
Overview & Philosophy
Target Abstraction & Host Decoupling
Target-to-Host Bridges
Bridge Deep Dive
Simulation Triggers
Optimizing FPGA Resource Utilization
Output Files
Developer Docs
Compiler & Driver Development
Complete FPGA Metasimulation
Visual Studio Code Integration
Managing the Conda Lock File
Manager Development
Miscellaneous
External Tutorial Setup
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Workloads
This section describes workload definitions in FireSim.
Workloads:
FireMarshal
[DEPRECATED] Defining Custom Workloads
Uniform Workload JSON
Non-uniform Workload JSON (explicit job per simulated node)
