FireSim generates SoC models by transforming RTL emitted by a Chisel generator, such as the Rocket SoC generator. Subject to conditions outlined in Restrictions on Target RTL, if it can be generated by Chisel, it can be simulated in FireSim.

Restrictions on Target RTL

Current limitations in MIDAS place the following restrictions on the (FIR)RTL that can be transformed and thus used in FireSim:

  1. The RTL must not contain multiple clock domains.
  2. The RTL must not contain multi-cycle paths.
  3. The RTL must not contain black boxes, with the exception of Rocket Chip’s async reset register.
  4. Asynchronous reset must only be implemented using Rocket Chip’s black box async reset. These are replaced with synchronously reset registers using a FIRRTL transformation.

Provided Target Designs

Target Generator Organization

FireSim provides multiple projects, each for a different type of target. Each project has it’s own chisel generator that invokes MIDAS, its own driver sources, and a makefrag that plugs into the Make-based build system that resides in sim/. These projects are:

  1. firesim (Default): rocket chip-based targets. These include targets with either BOOM or rocket pipelines, and should be your starting point if you’re building an SoC with the Rocket Chip generator.
  2. midasexamples: the MIDAS example designs, a set of simple chisel circuits like GCD, that demonstrate how to use MIDAS. These are useful test cases for bringing up new MIDAS features.
  3. fasedtests: designs to do integration testing of FASED memory-system timing models.

Projects have the following directory structure:

├-Makefile # Top-level makefile for projects where FireSim is the top-level repo
├-Makefrag # Target-agnostic makefrag, with recipes to generate drivers and RTL simulators
│                └─Makefrag # Defines target-specific make variables and recipes.
│             ├─{driver-csrcs}.cc # The target's simulation driver, and sofware-model sources
│             └─{driver-headers}.h
                     ├─Generator.scala # Contains the main class that generates target RTL and calls MIDAS

Specifying A Target Instance

To generate a specific instance of a target, the build system leverages four Make variables:

  1. TARGET_PROJECT: this points the Makefile (sim/Makefile) at the right target-specific Makefrag, which defines the generation and MIDAS-level software-simulation recipes. The makefrag for the default target project is defined at sim/src/main/makefrag/firesim.
  2. DESIGN: the name of the top-level Chisel module to generate (a Scala class name). For the default firesim target project, a common set of top-level modules is captured in sim/src/main/scala/firesim/Targets.scala.
  3. TARGET_CONFIG: specifies a Config instance that is consumed by the target design’s generator. For the default firesim target project, predefined configs are described in sim/src/main/scala/firesim/TargetConfigs.scala).
  4. PLATFORM_CONFIG: specifies a Config instance that is consumed by MIDAS and specifies simulation-land parameters, such as whether to enable assertion synthesis, how to assign endpoints to target I/O, and what sorts of endpoints to generate (ex. the specific FASED timing model instance to generate.). For the default firesim target project, predefined platform configs are described in sim/src/main/scala/firesim/SimConfigs.scala)

TARGET_CONFIG and PLATFORM_CONFIG are strings that are used to construct a Config instance (derives from RocketChip’s parameterization system, Config, see freechips.rocketchip.config). These strings are of the form “ClassName{_ClassName2}{_ClassName3}{_…}”. Only the first class name is compulsory, successive class names are prepended to the first to create a compound Config instance. See the example below:

// Specify by setting TARGET_CONFIG=Base
class Base extends Config((site, here, up) => {...})
class Override1 extends Config((site, here, up) => {...})
class Override2 extends Config((site, here, up) => {...})
// Specify by setting TARGET_CONFIG=Compound
class Compound extends Config(new Override2 ++ new Override1 ++ new Base)
// OR by setting TARGET_CONFIG=Base_Override1_Override2
// Can specify undefined classes this way. ex: TARGET_CONFIG=Base_Override2

With this scheme, you don’t need to define a Config class for every instance you wish to generate. We use this scheme to specify FPGA frequencies (eg. FireSimConfig_F90MHz) in manager build recipes, but it’s also very useful for doing sweeping over a parameterization space.

Rocket Chip Generator-based SoCs (firesim project)

Using the Make variables listed above, we give examples of generating different targets using the default Rocket Chip-based target project.

Rocket-based SoCs

Three design classes use Rocket scalar in-order pipelines.

Single core, Rocket pipeline (default)

make DESIGN=FireSim TARGET_CONFIG=FireSimRocketChipConfig

Single-core, Rocket pipeline, no network interface

make DESIGN=FireSimNoNIC TARGET_CONFIG=FireSimRocketChipConfig

Quad-core, Rocket pipeline

make DESIGN=FireSim TARGET_CONFIG=FireSimRocketChipQuadCoreConfig

BOOM-based SoCs

Two design classes use BOOM (Berkeley Out-of-Order Machine) superscalar out-of-order pipelines.

Single-core BOOM

make DESIGN=FireBoom TARGET_CONFIG=FireSimBoomConfig

Single-core BOOM, no network interface

make DESIGN=FireBoomNoNIC TARGET_CONFIG=FireSimBoomConfig

Generating A Different FASED Memory-Timing Model Instance

MIDAS’s memory-timing model generator, FASED, can elaborate a space of different DRAM model instances: we give some typical ones here. These targets use the Makefile-defined defaults of DESIGN=FireSim TARGET_CONFIG=FireSimRocketChipConfig.

Quad-rank DDR3 first-come first-served memory access scheduler


Quad-rank DDR3 first-ready, first-come first-served memory access scheduler


As above, but with a 4 MiB (maximum simulatable capacity) last-level-cache model


Midas Examples (midasexamples project)

This project can generate nine different target-designs (set with the make variable DESIGN), each of these designs has their own chisel source file. They include:

  1. EnableShiftRegister
  2. GCD
  3. Parity
  4. PointerChaser
  5. ResetShiftRegister
  6. Risc
  7. RiscSRAM
  8. ShiftRegister
  9. Stack

To generate MIDAS example targets, set the make variable TARGET_PROJECT=midasexamples. so that the right project makefrag is sourced.


Generate the GCD midas-example

make DESIGN=GCD TARGET_PROJECT=midasexamples

FASED Tests (fasedtests project)

This project generates target designs capable of driving considerably more bandwidth to an AXI4-memory slave than current FireSim-targets. Used used to do integration and stress testing of FASED instances.


Generate a synthesizable AXI4Fuzzer (based off of Rocket Chip’s TL fuzzer), driving a DDR3 FR-FCFS-based FASED instance.


As above, but with a fuzzer configue to drive 10 million transactions through the instance.