⚠️ We highly recommend using the XDMA-based U250 flow instead of this Vitis-based flow. You can find the XDMA-based flow here: Xilinx Alveo U250 XDMA-based Getting Started Guide. The Vitis-based flow does not support DMA-based FireSim bridges (e.g., TracerV, Synthesizable Printfs, etc.), while the XDMA-based flows support all FireSim features. If you’re unsure, use the XDMA-based U250 flow instead: Xilinx Alveo U250 XDMA-based Getting Started Guide

(Experimental) Xilinx Alveo U250 Vitis-based Getting Started Guide

The getting started guides that follow this page will walk you through the complete (Vitis-based) flow for getting an example FireSim simulation up and running using an on-premises Xilinx Alveo U250 FPGA, from scratch.

First, we’ll set up your environment, then run a simulation of a single RISC-V Rocket-based SoC booting Linux, using a pre-built bitstream. Next, we’ll show you how to build your own FPGA bitstreams for a custom hardware design. After you complete these guides, you can look at the “Advanced Docs” in the sidebar to the left.

Here’s a high-level outline of what we’ll be doing in this guide:

  1. FPGA Setup: Installing the FPGA board and relevant software.

  2. On-Premises Machine Setup

    1. Setting up a “Manager Machine” from which you will coordinate building and deploying simulations locally.

  3. Single-node simulation guide: This guide walks you through the process of running a simulation locally on a single Xilinx Alveo U250, using a pre-built, public bitstream.

  4. Building your own hardware designs guide (Chisel to FPGA Image): This guide walks you through the full process of taking Rocket Chip RTL and any custom RTL plugged into Rocket Chip and producing a FireSim bitstream to plug into your simulations. This automatically runs Chisel elaboration, FAME-1 Transformation, and the Xilinx Vitis FPGA flow.

Generally speaking, you only need to follow Step 4 if you’re modifying Chisel RTL or changing non-runtime configurable hardware parameters.